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The 8. 04. 86 processor has been on the market for more than 2. The pre- 5. 86 subset of the x. Registers. General purpose. BP and SP are not general- purpose. GPRs, including EBP and ESP6. GPRs, including RBP and RSPFloating point. FPU3. 2- bit: optional separate or integrated x. Jogos de motos online. Participe de corridas, faFPU, integrated SSE2 units in later processors. SSE2 units. Intel Core 2 Duo . The 8. 08. 6 was introduced in 1. Intel's 8- bit based 8. Today, however, x. This is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and probably also because the term became common after the introduction of the 8. A few years after the introduction of the 8. Get your files whenever you need right from your cellphone. Up to 10x better download speed. You should install it for sure. Download AMD Drivers & Software for Radeon, FirePro, APU, desktops and laptops. Intel added some complexity to its naming scheme and terminology as the . An 8. 08. 6 system, including coprocessors such as 8. Intel- specific system chips. Today, x. 86 is ubiquitous in both stationary and portable personal computers, and is also used in midrange computers, workstations, servers and most new supercomputerclusters of the TOP5. A large amount of software, including operating systems (OSs) such as DOS, Windows, Linux, BSD, Solaris and OS X, functions with x. Modern x. 86 is relatively uncommon in embedded systems, however, and small low power applications (using tiny batteries) as well as low- cost microprocessor markets, such as home appliances and toys, lack any significant x. Examples of this are the i. APX 4. 32 (a project originally named the . However, the continuous refinement of x. AMD's 6. 4- bit extension of x. Intel eventually responded to with a compatible design). Each line item is characterized by significantly improved or commercially successful processor microarchitecture designs. First introduced. Prominent CPU brands. Linear address size (bits)Segment / offset size (bits)Physical address size (bits)Notable (new) features. Intel 8. 08. 6, Intel 8. First x. 86 microprocessors. Intel 8. 01. 86, Intel 8. NEC V2. 0/V3. 01. Hardware for fast address calculations, fast multiplication and division. Intel 8. 02. 86 and clones. MMU, for protected mode and a larger address space. Intel 8. 03. 86 and clones, AMD Am. MMU with paging, PGA1. Intel 8. 04. 86 and clones, AMD Am. RISC- like pipelining, integrated x. FPU (8. 0- bit), on- chip cache, PGA1. Cyrix Cx. 48. 6SLC, Cyrix Cx. DLC3. 21. 4 / 3. 23. L1 cache and pipelining introduced into the 3. PGA1. 32 socket. 19. Pentium, Pentium MMX, Risem. P6. 32. 14 / 3. 23. Superscalar, 6. 4- bitdatabus, faster FPU, MMX (2. Such x. 86 implementations are seldom simple copies but often employ different internal microarchitectures as well as different solutions at the electronic and physical levels. Quite naturally, early compatible microprocessors were 1. For the personal computer market, real quantities started to appear around 1. Intel's original chips. Other companies, which designed or manufactured x. ITT Corporation, National Semiconductor, ULSI System Technology, and Weitek. Following the fully pipelinedi. Intel introduced the Pentium brand name (which, unlike numbers, could be trademarked) for their new set of superscalar x. IBM partnered with Cyrix to produce the 5x. M1) and 6x. 86. MX (MII) lines of Cyrix designs, which were the first x. AMD meanwhile designed and manufactured the advanced but delayed 5k. K5), which, internally, was closely based on AMD's earlier 2. KRISC design; similar to Nex. Gen's Nx. 58. 6, it used a strategy such that dedicated pipeline stages decode x. Some early versions of these microprocessors had heat dissipation problems. The 6x. 86 was also affected by a few minor compatibility problems, the Nx. FPU) and (the then crucial) pin- compatibility, while the K5 had somewhat disappointing performance when it was (eventually) introduced. Customer ignorance of alternatives to the Pentium series further contributed to these designs being comparatively unsuccessful, despite the fact that the K5 had very good Pentium compatibility and the 6x. Pentium on integer code. There were also other contenders, such as Centaur Technology (formerly IDT), Rise Technology, and Transmeta. VIA Technologies' energy efficient C3 and C7 processors, which were designed by the Centaur company, have been sold for many years. Centaur's newest design, the VIA Nano, is their first processor with superscalar and speculative execution. It was, perhaps interestingly, introduced at about the same time as Intel's first . In 1. 98. 5, Intel released the 3. Intel later dubbed it IA- 3. IA- 6. 4 architecture. In 1. 99. 9- 2. 00. AMD extended this 3. AMD6. 4. Intel soon adopted AMD's architectural extensions under the name IA- 3. EM6. 4T and finally using Intel 6. Microsoft and Sun Microsystems also use term . Microsoft Windows, for example, designates its 3. The instruction set is not typical CISC, however, but basically an extended version of the simple eight- bit 8. Byte- addressing is enabled and words are stored in memory with little- endian byte order. Memory access to unaligned addresses is allowed for all valid word sizes. The largest native size for integerarithmetic and memory addresses (or offsets) is 1. Multiple scalar values can be handled simultaneously via the SIMD unit present in later generations, as described below. Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single- byte). To further conserve encoding space, most registers are expressed in opcodes using three or four bits, the latter via an opcode prefix in 6. Among other factors, this contributes to a code size that rivals eight- bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8- bit ancestors) has made register- relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses, i. This microprocessor subsequently developed into the extended 8. In addition to this, modern x. SIMD- unit (see SSE below) where instructions can work in parallel on (one or two) 1. The presence of wide SIMD registers means that existing x. Intel's Sandy Bridge processors added the AVX (Advanced Vector Extensions) instructions. Knights Corner, the architecture used by Intel on their Xeon Phi co- processors, uses 5. SIMD registers. Current implementations. During execution, current x. These are then handed to a control unit that buffers and schedules them in compliance with x. These modern x. 86 designs are thus superscalar, and also capable of out of order and speculative execution (via register renaming), which means they may execute multiple (partial or complete) x. However, traditionalmicrocode (used since the 1. Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit. The latest processors also do the opposite when appropriate; they combine certain x. Another way to try to improve performance is to cache the decoded micro- operations, so the processor can directly access the decoded micro- operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in their Net. Burst Microarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core- branded processors since Sandy Bridge). They used just- in- time translation to convert x. CPU's native VLIW instruction set. Transmeta argued that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x. Segmentation. Minicomputers during the late 1. KB address limit, as memory had become cheaper. Some minicomputers like the PDP- 1. Digital's VAX, redesigned much more expensive processors which could directly handle 3. The original 8. 08. By multiplying a 6. KB address by 1. 6, the 2. The concept of segment registers was not new to many mainframes which used segment registers to swap quickly to different tasks. In practice, on the x. However, the architecture soon allowed linear 3. Microsoft) took several years to convert their 1. The 8. 03. 86 (and 8. Data and code could be managed within . While that would also prove to be quite limiting by the mid- 1. PC market, and made it very simple to translate software from the older 8. Z8. 0 to the newer processor. During 1. 98. 5, the 1. In real mode, segmentation is achieved by shifting the segment address left by 4 bits and adding an offset in order to receive a final 2. For example, if DS is A0. SI is 5. 67. 7h, DS: SI will point at the absolute address DS . Thus the total address space in real mode is 2. MB, quite an impressive figure for 1. All memory addresses consist of both a segment and offset; every type of access (code, data, or stack) has a default segment register associated with it (for data the register is usually DS, for code it is CS, and for stack it is SS). For data accesses, the segment register can be explicitly specified (using a segment override prefix) to use any of the four segment registers. In this scheme, two different segment/offset pairs can point at a single absolute location. Thus, if DS is A1. SI is 4. 56. 7h, DS: SI will point at the same A5. This scheme makes it impossible to use more than four segments at once. CS and SS are vital for the correct functioning of the program, so that only DS and ES can be used to point to data segments outside the program (or, more precisely, outside the currently executing segment of the program) or the stack. In protected mode, introduced in the 8. A segment descriptor contains the physical address of the beginning of the segment, the length of the segment, and access permissions to that segment. The offset is checked against the length of the segment, with offsets referring to locations outside the segment causing an exception. Offsets referring to locations inside the segment are combined with the physical address of the beginning of the segment to get the physical address corresponding to that offset. The segmented nature can make programming and compiler design difficult because the use of near and far pointers affects performance. Addressing modes. Addressing modes for 1. Only words (two bytes) can be pushed to the stack. The stack grows toward numerically lower addresses, with SS: SP pointing to the most recently pushed item. There are 2. 56 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return address. The original Intel 8. Four of them (AX, BX, CX, DX) are general- purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as a counter with the loop instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP (stack pointer) points to the . The registers SI, DI, BX and BP are address registers, and may also be used for array indexing. Four segment registers (CS, DS, SS and ES) are used to form a memory address. The FLAGS register contains flags such as carry flag, overflow flag and zero flag. Finally, the instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed; this register cannot be directly accessed (read or written) by a program. The 8. 08. 7 appears to the programmer as part of the CPU and adds eight 8. The 8. 02. 87 is the floating- point coprocessor for the 8. Registers available in the x. With the advent of the 3. FLAGS register, but not the segment registers, were expanded to 3. The nomenclature represented this by prefixing an . Thus, the AX register corresponds to the lowest 1. EAX register, SI corresponds to the lowest 1. ESI, and so on. The general- purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes. Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, the machine code format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 1. Special prefixes allow inclusion of 3. The 8. 03. 86 had an optional floating- point coprocessor, the 8. The 8. 03. 86 could also use an 8. An R- prefix identifies the 6. RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 6. R8- R1. 5) were also introduced in the creation of x. However, these extensions are only usable in 6. The addressing modes were not dramatically changed from 3. In addition, an addressing mode was added to allow memory references relative to RIP (the instruction pointer), to ease the implementation of position- independent code, used in shared libraries in some operating systems. SIMD registers XMM0. Holds the program counter, the current instruction address. Segment registers: CS: Code. DS: Data. SS: Stack. ES: Extra data. FS: Extra data #2. GS: Extra data #3. No particular purposes were envisioned for the other 8 registers available only in 6. Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as an accumulator and adding an immediate byte value to it produces the efficient add to ALopcode of 0. BL register produces the generic and longer add to register opcode of 8. C3h. Another example is double precision division and multiplication that works specifically with the AX and DX registers. Modern compilers benefited from the introduction of the sib byte (scale- index- base byte) that allows registers to be treated uniformly (minicomputer- like). However, using the sib byte universally is non- optimal, as it produces longer encodings than only using it selectively when necessary. A notable example is the LODSW instruction. Structure. General Purpose Registers (A, B, C and D)6. R? XE? X ? X ? H ? L6. 4- bit mode- only General Purpose Registers (R8, R9, R1. R1. 1, R1. 2, R1. R1. 4, R1. 5)6. 45. Real mode is characterized by a 2. Mi. B of memory can be addressed. All x. 86 CPUs in the 8. CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips. However, this is not a characteristic of the x. CPU but of the IBM BIOS design.)In order to use more than 6. KB of memory, the segment registers must be used. This created great complications for compiler implementors who introduced odd pointer modes such as . It is technically possible to use up to 2. KB of memory for code and data, with up to 6. KB for code, by setting all four segment registers once and then only using 1. Intel designers, which is for separate data items (e. This is done by using the segment registers only for storing an index into a descriptor table that is stored in memory. There are two such tables, the Global Descriptor Table (GDT) and the Local Descriptor Table (LDT), each holding up to 8. KB of memory. In the 8. The base address from the table fulfills the same role that the literal value of the segment register fulfills in real mode; the segment registers have been converted from direct registers to indirect registers. Each segment can be assigned one of four ring levels used for hardware- based computer security. Each segment descriptor also contains a segment limit field which specifies the maximum offset that may be used with the segment. Because offsets are 1. KB each in 8. 02. Therefore, loading segment registers is much slower in protected mode than in real mode, and changing segments very frequently is to be avoided. Actual memory operations using protected mode segments are not slowed much because the 8. The Intel 8. 03. 86 extended offsets and also the segment limit field in each segment descriptor to 3. It also introduced support in protected mode for paging, a mechanism making it possible to use paged virtual memory (with 4 KB page size). Paging allows the CPU to map any page of the virtual memory space to any page of the physical memory space. To do this, it uses additional mapping tables in memory called page tables. Protected mode on the 8. The segmentation mechanism can also be effectively disabled by setting all segments to have a base address of 0 and size limit equal to the whole address space; this also requires a minimally- sized segment descriptor table of only four descriptors (since the FS and GS segments need not be used). Linux, 3. 86. BSD and Windows NT were developed for the 3. Intel architecture CPU to support paging and 3. The 3. 86 architecture became the basis of all further development in the x. Operating system boot code, which might be stored in ROM, may place the processor into the protected mode to enable paging and other features. The instruction set in protected mode is backward compatible with the one used in real mode. Virtual 8. 08. 6 mode. There is also a sub- mode of operation in 3. V8. 6 mode. This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a protected mode supervisor operating system. This allows for a great deal of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is exclusively available for the 3. Long mode. In the mid 1. A 3. 2- bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such as video processing and database engines. Using 6. 4- bit addresses, it is possible to directly address 1. Ei. B of data, although most 6. AMD6. 4 supports only 4. In 1. 99. 9, AMD published a (nearly) complete specification for a 6. That design is currently used in almost all x. Mass- produced x. AMD6. 4. The success of the AMD6. IA- 6. 4 architecture forced Intel to release its own implementation of the AMD6. Intel had previously implemented support for AMD6. It branded its implementation of AMD6. EM6. 4T, and later re- branded it Intel 6. In its literature and product version names, Microsoft and Sun refer to AMD6. Intel 6. 4 collectively as x. Windows and Solaris operating systems respectively. Linux distributions refer to it either as . This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work. This was the first time that a major extension of the x. Intel. It was also the first time that Intel accepted technology of this nature from an outside source. Extensions. Floating point unit. Early x. 86 processors could be extended with floating- point hardware in the form of a series of floating point numericalco- processors with names like 8. This was also known as the NPX (Numeric Processor e. Xtension), an apt name since the coprocessors, while used mainly for floating- point calculations, also performed integer operations on both binary and decimal formats. With very few exceptions, the 8. Each x. 87 register, known as ST(0) through ST(7), is 8. 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